1. Field of the Invention
The present invention relates to a transmission line encoding/decoding system for preventing more than a predetermined number of "0" bits from appearing in series in digital data delivered to a transmission line.
2. Description of the Prior Art
In a communication system of the type in which timing information is extracted from digital data received from a transmission line to set an operating clock on the basis of the timing information thus obtained, if an excess number of "0" bits appear in series in the data received from the transmission line, timing information cannot be extracted at the receiving side and it is therefore necessary to limit the number of "0" bits delivered in series at the transmitting side. For instance, AT&T Publication 62411, U.S.A., specifies the state of a series of "0" bits as follows:
(1) a series of 16 or more "0" bits must not be delivered PA1 (2) at least n "1" bits must be contained in a range of 8.times.(n+1) bits at any time (n=1 to 23)
Under these circumstances, it has heretofore been common practice to prevent transmission of an excess number of "0" bits in series by use of a technique known as bit-7 stuffing, such as that shown in the application note (Document No. 29300N23, Order No. 323, September 1986) of LSIR8070 manufactured by Rockwell. According to the bit-7 stuffing technique, data to be transmitted is monitored for each slot (1 slot=8 bits), and when all the data bits in a slot are "0", the 7th bit in the slot is forcibly set to "1" and the data is transmitted in this state, thereby satisfying the above-described limiting conditions. FIG. 28 illustrates the encoding process by the bit-7 stuffing technique, in which: FIG. 28(a) shows data to be transmitted which is in the pre-processing state, FIG. 28(b) shows a transmitting clock signal, and FIG. 28(c) shows data transmitted to the transmission line after the bit-7 stuffing processing. The data shown in FIG. 28(c) is transmitted in synchronism with the rise of the transmitting clock signal shown in FIG. 28(b). Each slot comprises 8 bits, and 24 slots constitute a combination 1 frame. A frame bit F is added to the top of each frame. FIG. 28 shows a part of the transmitted data, that is, from slot 23 in one frame to the top of slot 1 in the next frame. As will be clear from FIG. 28, the bit stuffing processing is conducted in such a manner that data to be transmitted which is in the pre-processing state is monitored for each slot, and if a slot contains at least one "1" bit, as in the case of slot 23, the slot is transmitted in this state, whereas, if all the bits of a slot are "0", as in the case of slot 24, the 7th bit B7 in the slot is forcibly changed to "1" to obtain the transmitted data as shown in FIG. 28(c), thereby satisfying the above-described conditions of limiting the number of "0" bits delivered in series.
The conventional transmission line encoding/decoding system suffers, however, from the following problems. In the prior art, when all the bits of any slot are "0", a predetermined bit is forcibly changed to "1" at the transmitting side, as described above, and therefore a slot in which a predetermined bit has been forcibly changed to "1" because all the original data bits were "0" has the same form as that of a slot in which only a predetermined bit is originally "1", so that it is impossible to discriminate these two slots from each other at the data receiving side, which results in a data error. Accordingly, it is necessary in order to realize transparent data transmission to reserve a predetermined bit in every slot for bit stuffing. In consequence, the actual data transmitting speed is lower than the rated transmitting speed of the transmission line. For example, if one slot comprises 8 bits, the data transmitting speed is limited to 7/8 of the transmitting speed of the transmission line, resulting in a lowering of the channel occupancy ratio.